Atomic layer deposition and physical vapor deposition bilayer for additive patterning

ABSTRACT

A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

BACKGROUND

Cognitive (e.g., memory) devices may contain materials that cannot be dry etched in fabrication facilities via reactive ion etching (ME) due to safety and chamber contamination concerns. Such materials can include, for example, phase change material (PCM), such as germanium-antimony-tellurium (GeSbTe), ovonic threshold switch (OTS) material including, for example, silicon germanium arsenide selenide (SiGeAsSe), and electrochemical metallization (ECM) material, such as AgGeSe. Additive patterning integrations allow capping these materials with a conductive electrode.

Physical vapor deposition (PVD) is a facile way to deposit metal/metal nitrides forming the conductive electrodes at low temperatures which are compatible with low-temperature technologies. However, PVD deposited films often damage common dielectrics (e.g., low-k dielectrics) that surround the memory materials (e.g., memory elements). Subsequent wet processing from additive patterning integration often removes the damaged dielectric, leading to unwanted recesses in the dielectric layer adjacent to the conductive electrodes. The recesses in the dielectric layer can expose sensitive memory elements to the environment, which can negatively impact device performance.

Accordingly, there is a need for techniques to form electrodes on memory materials which allows for low temperature processing while avoiding damage to surrounding dielectric layers.

SUMMARY

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element.

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a phase change material in a dielectric layer, and forming a bottom electrode under the phase change material. In the method, a conductive liner layer is deposited on the dielectric layer and the phase change material by atomic layer deposition, and a conductive layer is deposited on the conductive liner layer. The method further includes patterning the conductive liner layer and the conductive layer into a top electrode on the phase change material.

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a contact in a first dielectric layer, and forming a bottom electrode on the contact. In the method, a second dielectric layer including a low-k dielectric is formed on the first dielectric layer. A memory element is formed on the bottom electrode, and is surrounded by the second dielectric layer. The method further includes depositing by atomic layer deposition a first conductive layer on the second dielectric layer and the memory element, and depositing a second conductive layer on the first conductive layer. The first and second conductive layers are patterned into a top electrode on the memory element.

These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be described below in more detail, with reference to the accompanying drawings, of which:

FIG. 1 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing deposition of an electrode bilayer, according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing deposition of a trilayer mask structure and a resist, according to an embodiment of the invention.

FIG. 3 is a schematic cross-sectional views illustrating manufacturing of a semiconductor device and showing patterning of the trilayer mask structure, according to an embodiment of the invention.

FIG. 4 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing removal of two uppermost layers of the mask structure, according to an embodiment of the invention.

FIG. 5 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing patterning of the electrode bilayer under a hardmask layer, according to an embodiment of the invention.

FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device manufactured according to an embodiment of the invention.

FIG. 7 is an image of a semiconductor device manufactured according to an embodiment of the invention.

DETAILED DESCRIPTION

Exemplary embodiments of the invention will now be discussed in further detail with regard to semiconductor devices and methods of manufacturing same and, in particular, to methods and structures to prevent recessing (e.g., gouge) in a dielectric layer surrounding a storage element, while still gaining the electrical benefits of using low-k materials for memory elements.

It is to be understood that the various layers and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and/or regions of a type commonly used in, for example, phase-change memory (PCM), phase-change random-access memory (PCRAM), resistive random-access memory (RRAM or ReRAM), three-dimensional (3D) RRAM, magnetic random-access memory (MRAM), fuse/anti-fuse, diode, ovonic threshold switch (OTS), bipolar junction transistor (BJT), complementary metal-oxide semiconductor (CMOS), field-effect transistor (FET), nanowire FET, nanosheet FET, fin field-effect transistor (FinFET), metal-oxide-semiconductor field-effect transistor (MOSFET) and/or other semiconductor devices may not be explicitly shown in a given drawing. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual devices. In addition, certain elements may be left out of particular views for the sake of clarity and/or simplicity when explanations are not necessarily focused on the omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings.

The semiconductor devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

The embodiments of the present invention can be used in connection with semiconductor devices that may require, for example, PCM, PCRAM, RRAM, 3D RRAM, MRAM, fuses/anti-fuses, diodes, OTSs, BJTs, FETs, CMOSs, MOSFETs, nanowire FETs, nanosheet FETs and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to PCM, PCRAM, RRAM, 3D RRAM, MRAM, fuse/anti-fuse, diode, OTS, BJT, FET, CMOS, MOSFET, nanowire FET, nanosheet FET and FinFET devices, and/or semiconductor devices that use PCM, PCRAM, RRAM, 3D RRAM, MRAM, fuse/anti-fuse, diode, OTS, BJT, FET, CMOS, MOSFET, nanowire FET, nanosheet FET and/or FinFET technology.

As used herein, “height” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views or images measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located. Conversely, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views or images measured from a top surface to a bottom surface of the element.

As used herein, “lateral,” “lateral side,” “lateral surface” refers to a side surface of an element (e.g., a layer, opening, etc.), such as a left or right side surface in the drawings.

As used herein, “width” or “length” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element.

As used herein, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. For example, as used herein, “vertical” refers to a direction perpendicular to the top surface of a layer or substrate in the cross-sectional views or images, and “horizontal” refers to a direction parallel to the top surface of a layer or substrate in the cross-sectional views or images.

As used herein, unless otherwise specified, terms such as “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element is present on a second element, wherein intervening elements may be present between the first element and the second element. As used herein, unless otherwise specified, the term “directly” used in connection with the terms “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” or the term “direct contact” mean that a first element and a second element are connected without any intervening elements, such as, for example, intermediary conducting, insulating or semiconductor layers, present between the first element and the second element.

As used herein, “low-k” refers to dielectric materials having a relative dielectric constant less than 7, and includes ultra-low-k dielectric materials.

As used herein, “high-k” refers to dielectric materials having a relative dielectric constant greater than 7.

In accordance with an embodiment of the present invention, an atomic layer deposition (ALD) film is deposited on a memory element (e.g., PCM, OTS, etc.) and a surrounding dielectric layer in which the memory element is formed. The ALD film is deposited between the dielectric layer and a subsequently deposited physical vapor deposition (PVD) film in order to protect the underlying dielectric layer from damage which can occur during patterning of the PVD film into a top electrode on the memory element. A bilayer of the PVD deposited film on the ALD deposited film is patterned into a top electrode on the memory element without damage to (e.g., unwanted recessing) of the dielectric layer. As a result of the dielectric layer remaining intact due to the protection afforded by the ALD film, the memory element is not exposed to the environment, and device degradation is prevented.

FIG. 1 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing deposition of an electrode bilayer, according to an embodiment of the invention. Referring to FIG. 1, a semiconductor device 100 includes a plurality of conductive landing pads 106 (e.g., contacts) formed in a dielectric layer 104. The dielectric layer 104 includes, for example, tetraethyl orthosilicate (TEOS), silicon dioxide (SiO₂), carbon-doped silicon oxide (SiCOH), SiLK® dielectrics, and/or porous forms of these low-k dielectric films.

As can be understood by one of ordinary skill in the art, the dielectric layer 104 can be on a semiconductor substrate 102, with intervening layers (e.g., lower conductive lines, devices, etc.) between the dielectric layer 104 and the substrate 102. A semiconductor substrate 102 may comprise semiconductor material including, but not limited to, Si, SiGe, SiC, SiGeC or other like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate 102. A plurality of devices can be on the substrate 102, such as, for example, transistors, capacitors, and resistors.

A liner layer 108 comprising, for example titanium nitride, tantalum nitride or tungsten nitride is conformally formed on the sidewalls and bottom surfaces of trenches in which the landing pads 106 are formed. The landing pads 106 include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides or combinations thereof deposited on the liner layers 108 using deposition techniques, including, but not necessarily limited to, PVD, chemical vapor depositions (CVD), ALD or sputtering. In accordance with an embodiment of the present invention, the landing pads 106 can be electrically connected to or form contact lines, such as, for example, wordlines, of a resulting memory cell array. The number of landing pads 106 shown in the figures is illustrative, and the embodiments of the present invention are not necessarily limited to the number of landing pads shown.

As shown in FIG. 1, another dielectric layer 110 is formed on the dielectric layer 104 including the landing pads 106. The dielectric layer 110 includes, for example, SiO₂, SC6 silicon nitride (SiN), and has a thickness (e.g., vertical height) in the range of about 10 nm-about 40 nm, for example, about 20 nm. Another dielectric layer 115 includes, for example, NBLoK™ material from Applied Materials, Inc. of Santa Clara, Calif., which is a nitrogen-doped silicon carbide. The dielectric layer 115 is formed on the dielectric layer 110 using deposition techniques, including, but not necessarily limited to, PVD, CVD, ALD or sputtering. A thickness (e.g., vertical height) of the dielectric layer 115 is in the range of about 20 nm to about 30 nm.

A low-k dielectric layer 120 is formed on the dielectric layer 115 using, for example, deposition techniques, including, but not necessarily limited to, PVD, CVD, ALD or sputtering. According to an embodiment of the present invention, the low-k dielectric layer 120 includes, for example, TEOS, SiO₂, SiCOH, SiLK® dielectrics, and/or porous forms of these low-k dielectric films. A thickness (e.g., vertical height) of the low-k dielectric layer 120 is in the range of about 100 nm to about 120 nm.

As can be seen in FIG. 1, a memory element 116 including, for example, PCM (e.g. Ge₂Sb₂Te₅), OTS material (e.g. SiTe, ZnTe, As₂Te₃) and/or ECM material (e.g. LiCoO₂, Li₄Ti₅O₁₂) is formed through the dielectric layers 120 and 115 and contacts a bottom electrode 112 embedded in the dielectric layer 110.

The memory element 116 is deposited in a trench surrounded by the dielectric layers 120 and 115 and lined on side and bottom surfaces with a liner layer 118 including, for example, TaN or TiN deposited using techniques such as ALD or PVD. According to an embodiment of the present invention, a horizontal width of the bottom electrode is in the range of about 36 nm to about 56 nm, and includes, for example, TaN. A thickness of the bottom electrode is the same or substantially the same as a thickness of the dielectric layer 115, and the bottom electrode 112 is in electrical contact with the memory element 116 and a corresponding landing pad 106.

According to an embodiment of the present invention, a conductive liner layer 125 including, for example, ALD TaN, is deposited on the low-k dielectric layer 120 including the memory element 116 formed therein. The liner layer 125 can also be formed from ALD TiN or other conductive nitride, as long as the liner layer is an ALD film with low reactivity. The liner layer 125 has a thickness (e.g., vertical height) in the range of about 3 nm to about 5 nm so as to limit the liner layer 125 from contributing to a resistance of the device 100. The liner layer 125 is deposited using ALD. A conductive layer 130 is formed on the conductive liner layer 125. In accordance with an embodiment of the present invention, the conductive layer 130 includes, for example, PVD TaN or a PVD TiN/TaN bilayer, and has a thickness (e.g., vertical height) in the range of about 20 nm to about 30 nm. The conductive layer 130 is deposited using PVD. As noted herein, the liner layer 125 functions as a protective layer for the low-k dielectric layer 120 to protect the underlying low-k dielectric layer 120 from damage which can occur during patterning of the PVD conductive layer 130 on the liner layer 125 into a top electrode of the memory element 116.

FIG. 2 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing deposition of a trilayer mask structure and a resist, according to an embodiment of the invention. Referring to FIG. 2, a trilayer mask structure includes a hardmask layer 135 formed on the conductive layer 130, an organic planarization layer (OPL) 140 formed on the hardmask layer and a silicon anti-reflective coating (SiARC) layer 145 formed on the OPL 140.

According to an embodiment of the present invention, the hardmask layer 135 includes, for example, SiN, silicon boron nitride (SiBN), siliconborocarbonitride (SiBCN) and/or silicon oxycarbonitride (SiOCN) and has a thickness (e.g., vertical height) in the range of about 50 nm-about 200 nm. The hardmask layer 135 is deposited by one or more deposition techniques, including, but not necessarily limited to, PVD, CVD, ALD or sputtering.

The OPL 140 comprises, but is not necessarily limited to, an organic polymer including C, H, and N. In an embodiment, the OPL material can be free of silicon (Si). According to an embodiment, the OPL material can be free of Si and fluorine (F). As defined herein, a material is free of an atomic element when the level of the atomic element in the material is at or below a trace level detectable with analytic methods available in the art. Non-limiting examples of the OPL material include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials from such vendors as JSR, TOK, Sumitomo, Rohm & Haas, etc. The OPL 140 can be deposited, for example, by spin coating, to a thickness of about 100 nm-about 200 nm. The SiARC layer 145 is deposited on the OPL 140.

A resist 150 is formed on the SiARC layer 145 over the memory element 116. The resist has a thickness in the range of about 80 nm to about 110 nm, and horizontal width which corresponds to that of the bottom electrode 112 and the memory element 116.

FIG. 3 is a schematic cross-sectional views illustrating manufacturing of a semiconductor device and showing patterning of the trilayer mask structure, according to an embodiment of the invention. Referring to FIG. 3, the trilayer mask structure including the stacked structure of the hardmask layer 135, the OPL 140 and the SiARC layer 145 is patterned by an etching process, which removes portions of the mask structure not covered by the resist 150. The etch process is performed using, for example, a fluorocarbon RIE to remove exposed portions of the trilayer mask structure down to the conductive layer 130.

FIG. 4 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing removal of two uppermost layers of the mask structure, according to an embodiment of the invention. Referring to FIG. 4, the OPL 140 and the SiARC layer 145 are removed from the hardmask layer 135 using, for example, oxygen plasma, nitrogen plasma, hydrogen plasma or other carbon strip or ashing process. The stripping process causes minimal or no damage to the remaining layers. As can be seen in FIG. 4, the patterned hardmask layer 135 remains covering the device area corresponding to the memory element 116 and the bottom electrode 112.

FIG. 5 is a schematic cross-sectional view illustrating manufacturing of a semiconductor device and showing patterning of the electrode bilayer under a hardmask layer, according to an embodiment of the invention. Referring to FIG. 5, the conductive layer 130 and the underlying conductive liner layer 125 are patterned by a chlorine-based dry etching process (as shown by the arrows) into an electrode bilayer comprising the remaining portions of the conductive layer 130 (e.g., PVD TaN) and the conductive liner layer (e.g., ALD TaN) under the hardmask layer 135. The patterned layers 130 and 125 form a top electrode for the memory element 116 in a stacked bilayer structure. A thickness of the hardmask layer 135 is reduced as a result of the etching process, and following the etching, the hardmask layer 135 can be removed using, for example, diluted hydrofluoric acid (DHF). As illustrated in FIG. 5, due to the protection afforded by the ALD liner layer 125, the dielectric layer 120 remains intact and does not include unwanted recesses following subtractive patterning of the stacked structure of the conductive layer 130 and the conductive liner layer 125 into the top electrode structure. The subtractive patterning removes exposed portions of the conductive layer 130 and the conductive liner layer 125.

Subsequent downstream processing can be performed to form a contact to the top electrode structure comprising the layers 130 and 125. As can be understood, although one memory element is illustrated, the embodiments of the present invention are not necessarily limited thereto, and more than one memory element 116 and corresponding electrode bilayer structure can be formed by the techniques and processes according to embodiments of the present invention.

FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device manufactured according to an embodiment of the invention. Referring to FIG. 6, a device 200 is similar to the device 100 and includes similar reference numbers to FIGS. 1-5 referring to similar elements. For example, like the device 100, device 200 includes a plurality of landing pads 206 deposited on liner layers 208 in trenches formed in a dielectric layer 204. Building up from the dielectric layer 204, device 200 has a similar structure to device 100 including dielectric layer 210, and dielectric layers 215 and 220. Device 200 illustrates two memory elements 216 formed on liner layers 218 in trenches through the dielectric layers 220 and 215 and connected to respective bottom electrodes 212 embedded in the dielectric layer 210. The device 200 further includes two top electrode structures each comprising a PVD conductive layer 230 and an underlying protective ALD conductive liner layer 225 corresponding to a memory element 216. As can be seen in FIG. 6, due to the protection afforded by the ALD liner layers 225, the dielectric layer 220 remains intact and does not include unwanted recesses following subtractive patterning of the stacked structure of the conductive layer 230 and the conductive liner layer 225 into the top electrode structures.

In addition to the metallization level including landing pads 206 in dielectric layer 204, device 200 further illustrates another metallization level below the landing pads 206 including a landing pad 205 (e.g., contact) formed on a liner 207 in a trench in a dielectric layer 203 including the same or similar materials as the dielectric layer 204. The landing pad 205 and liner 207 can include the same or similar materials as those of the landing pad and liner 206 and 208.

FIG. 6 shows three regions R1, R2 and R3 respectively referring to a logic region with no backend device (R1), a fill region with unconnected devices (e.g., not connected to landing pad 205) (R2), and a connected device region (e.g., connected to landing pad 205) (R3). The devices can include, but are not necessarily limited to, PCM, OTS and ECM devices.

FIG. 7 is an image of a semiconductor device manufactured according to an embodiment of the invention. Referring to FIG. 7, a device 300 is similar to the devices 100 and 200 and includes similar reference numbers to FIGS. 1-6 referring to similar elements. For example, like the devices 100 and 200, device 300 includes a plurality of landing pads 306 deposited on liner layers (not visible in FIG. 7) in trenches formed in a dielectric layer 304. Building up from the dielectric layer 304, device 300 has a similar structure to devices 100 and 200 including dielectric layer 310, and dielectric layers 315 and 320. Device 300 illustrates two memory elements 316 formed in trenches through the dielectric layers 220 and 215 and connected to respective bottom electrodes 312 embedded in the dielectric layer 310. The device 300 further includes two top electrode structures 330/325 each comprising a PVD conductive layer and an underlying protective ALD conductive liner layer (distinction between layers 330 and 325 not visible in FIG. 7) corresponding to a memory element 316. As can be seen in FIG. 7, due to the protection afforded by the ALD liner layers, the dielectric layer 220 remains intact and does not include unwanted recesses following subtractive patterning of the stacked structure of the conductive layer and the conductive liner layer into the top electrode structures 325/330.

Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention. 

1. A method for manufacturing a semiconductor device, comprising: forming a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a memory element in the second and third dielectric layers; depositing by atomic layer deposition a first conductive layer on the third dielectric layer and the memory element; depositing by physical vapor deposition a second conductive layer on the first conductive layer; and patterning the first and second conductive layers into an electrode on the memory element; wherein the second dielectric layer comprises silicon carbide; and wherein the third dielectric layer comprises a different material from the second dielectric layer.
 2. The method according to claim 1, wherein the patterning comprises performing a subtractive process which removes portions of the first and second conductive layers.
 3. The method according to claim 1, wherein the first conductive layer comprises tantalum nitride (TaN).
 4. The method according to claim 3, wherein a thickness of the first conductive layer is in a range about 3 nm to about 5 nm.
 5. The method according to claim 4, wherein the second conductive layer comprises TaN.
 6. The method according to claim 5, wherein a thickness of the second conductive layer is in a range about 20 nm to about 30 nm.
 7. The method according to claim 1, wherein the memory element comprises at least one of a phase change material, an ovonic threshold switch and electrochemical metallization material.
 8. The method according to claim 1, further comprising forming a bottom electrode in the first dielectric layer under the memory element and on an underlying contact, wherein a width of the bottom electrode is less than a width of the underlying contact.
 9. The method according to claim 1, further comprising forming a mask structure on the second conductive layer.
 10. The method according to claim 9, wherein forming the mask structure comprises: forming a nitride layer on the second conductive layer; forming an organic planarization layer on the nitride layer; and forming a silicon anti-reflective coating layer on the organic planarization layer.
 11. The method according to claim 10, further comprising: forming a resist covering a first portion of the mask structure; and removing a second portion of the mask structure not covered by the resist.
 12. The method according to claim 9, further comprising patterning the mask structure so that the patterned mask structure covers a first region of the first and second conductive layers formed over the memory element, and exposes a second region of the first and second conductive layers.
 13. The method according to claim 12, wherein the patterning of the first and second conductive layers into the electrode comprises removing the exposed second region of the first and second conductive layers.
 14. The method according to claim 13, wherein the removing exposes portions of the third dielectric layer under the second region of the first and second conductive layers.
 15. The method according to claim 1, wherein the second dielectric layer comprises nitrogen-doped silicon carbide.
 16. A method for manufacturing a semiconductor device, comprising: forming a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a phase change material in the second and third dielectric layers; forming a bottom electrode in the first dielectric layer under the phase change material; depositing by atomic layer deposition a conductive liner layer on the third dielectric layer and the phase change material; depositing a conductive layer on the conductive liner layer; and patterning the conductive liner layer and the conductive layer into a top electrode on the phase change material; wherein the second dielectric layer comprises silicon carbide; and wherein the third dielectric layer comprises a different material from the second dielectric layer.
 17. The method according to claim 16, wherein the patterning comprises performing a subtractive process which removes portions of the conductive liner layer and the conductive layer.
 18. The method according to claim 16, wherein the conductive layer is deposited on the conductive liner layer by physical vapor deposition.
 19. A method for manufacturing a semiconductor device, comprising: forming a contact in a first dielectric layer; forming a bottom electrode on the contact; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer comprises a low-k dielectric; forming a memory element on the bottom electrode, wherein the memory element is surrounded by the second and third dielectric layers; depositing by atomic layer deposition a first conductive layer on the third dielectric layer and the memory element; depositing a second conductive layer on the first conductive layer; and patterning the first and second conductive layers into a top electrode on the memory element; wherein the second dielectric layer comprises silicon carbide; and wherein the third dielectric layer comprises a different material from the second dielectric layer.
 20. The method according to claim 19, wherein the patterning comprises performing a subtractive process which removes portions of the first and second conductive layers. 